Hardware API - SC12 @CHIP-RTOS V1.10

IPC@CHIP Documentation Index Hardware API News

Here are the interface definitions for access to the IPC@CHIP's hardware.

Topics

API Functions

The hardware API uses interrupts 0xA2 (PFE functions) and 0xA1 (HAL functions) with a service number in the high order byte of the AX register (AH). The implemented hardware services are listed below.

For some useful comments see also under Programming notes

Interrupt_0xA2_function_0x80:_PFE: Enable Data Bus

Interrupt_0xA2_function_0x81:_PFE: Enable Non-Multiplexed Address Bus

Interrupt_0xA2_function_0x82:_PFE: Enable Programmable I/O Pins

Interrupt_0xA2_function_0x83:_PFE: Enable Programmable Chip Selects

Interrupt_0xA2_function_0x84:_PFE: Enable External Interrupt Requests

Interrupt_0xA2_function_0x85:_PFE: Enable External Timer Inputs/Outputs

Interrupt_0xA2_function_0x86:_PFE: Set Edge/Level Interrupt Mode

Interrupt_0xA2_function_0x87:_PFE: Enable PWD Mode

Interrupt_0xA2_function_0x88:_PFE: Enable External DMA

Interrupt_0xA2_function_0x89:_PFE: Enable INT0 / INTA cascade mode

Interrupt_0xA2_function_0x8A:_PFE: Set wait states for PCS0-3

Interrupt_0xA2_function_0x90:_PFE: Get Hardware API Function Pointers

Interrupt_0xA1_function_0x10:_HAL: Set int0 Vector

Interrupt_0xA1_function_0x80:_HAL: Read Data Bus

Interrupt_0xA1_function_0x81:_HAL: Write Data Bus

Interrupt_0xA1_function_0x82:_HAL: Read Programmable I/O Pins

Interrupt_0xA1_function_0x83:_HAL: Write Programmable I/O Pins

Interrupt_0xA1_function_0x84:_HAL: Install Interrupt Service Routine

Interrupt_0xA1_function_0x85:_HAL: Initialize Timer Settings

Interrupt_0xA1_function_0x86:_HAL: Start Timer

Interrupt_0xA1_function_0x87:_HAL: Stop timer

Interrupt_0xA1_function_0x88:_HAL: Read Timer Count

Interrupt_0xA1_function_0x89:_HAL: Write Timer Count

Interrupt_0xA1_function_0x8A:_HAL: Get Frequencies

Interrupt_0xA1_function_0x8B:_HAL: Set Timer Duty Cycle Waveform

Interrupt_0xA1_function_0x8C:_HAL: Read Specific I/O Pin

Interrupt_0xA1_function_0x8D:_HAL: Write to Specific I/O Pin

Interrupt_0xA1_function_0x8E:_HAL: Give EOI

Interrupt_0xA1_function_0x8F:_HAL: Initialize Timer Settings Ext

Interrupt_0xA1_function_0x90:_HAL: Get/Set Watchdog Mode

Interrupt_0xA1_function_0x91:_HAL: Refresh Watchdog

Interrupt_0xA1_function_0x92:_HAL: Mask/Unmask Int

Interrupt_0xA1_function_0xA0:_HAL: Block Read Data Bus

Interrupt_0xA1_function_0xA1:_HAL: Block Write Data Bus

Interrupt_0xA1_function_0xB0:_HAL: Start DMA Mode

Interrupt_0xA1_function_0xB1:_HAL: Stop DMA Transfer

Interrupt_0xA1_function_0xB2:_HAL: Get DMA Info

Interrupt_0xA1_function_0xC0:_HAL: Initialize/Restore Non-Volatile Data

Interrupt_0xA1_function_0xC1:_HAL: Save Non-Volatile Data

Interrupt_0xA1_function_0xC2:_HAL: Get Reboot Reason

Interrupt 0xA2 service 0x80: PFE: Enable Data Bus

Initialize data bus I/O mask and ALE usage.

Parameters

AH

Must be 0x80.

AL

0: Disable ALE, 1: Enable ALE

DX

Mask

Return Value

none

Comments

The I/O mask defines which data bits on the bus are inputs and which are outputs.   The DX mask bit for bi-directional data bus lines (read/write) should be set to '1'.

used pins:
    ALE, AD[0..7], RD#, WR#
excluded pins:
    if ALE is used, then PCS0# is not available.

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Interrupt 0xA2 service 0x81: PFE: Enable Non-Multiplexed Address Bus

The IPC@CHIP has three non-multiplexed address bit outputs, A0 through A2. The enabling of these pins is done here.

Parameters

AH: Must be 0x81.
DX: Mask
    Bit 0 = 1 Enable A0
    Bit 1 = 1 Enable A1
    Bit 2 = 1 Enable A2
    Bit 3..15 not used

Return Value

none

Comments

used pins:
    A[0..2], AD[0..7], RD#, WR#
excluded pins:
    If A0 is enabled then PCS1#, TMRIN0, PIO4 are not available
    If A1 is enabled then PCS[5..6]#, TMRIN1, TMROUT1, PIO3 are not available
    If A2 is enabled then PCS[5..6]#, PIO2 are not available.

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Interrupt 0xA2 service 0x82: PFE: Enable Programmable I/O Pins

Enable used programmable I/O pins. Define which pins are inputs and which are outputs.

Parameters

AH

Must be 0x82.

AL

Mode

DX

PIO pin

Return Value

AX = wPIO

DX = wINPUTS (all pins, including non-PIO pins)

CX = wOUTPUTS (all pins, including non-PIO pins)

AX = DX = CX = 0, Error: Wrong arguments

Comments

This function can be called several times for definition of different PIO pins.   With repeated selection of the same pin, the definition made last is valid.   The selection of a PIO pin can be cancelled by calling the appropriate PFE function that causes the respective PIO pin to be used for another purpose (e.g. function 0x83 for PIO[2..6] pins).

used pins:
    PIO[0..13]
excluded pins:
    All other functionality on the selected PIO pin.

Parameters

AH: Must be 0x83.
DX: Mask
    Bit 0 = 1 Enable PCS0#, active when I/O address between 000h..0FFh
    Bit 1 = 1 Enable PCS1#, active when I/O address between 100h..1FFh
    Bit 2 = 1 Enable PCS2#, active when I/O address between 200h..2FFh
    Bit 3 = 1 Enable PCS3#, active when I/O address between 300h..3FFh
    Bit 4 = don't care
    Bit 5 = 1 Enable PCS5#, active when I/O address between 500h..5FFh
    Bit 6 = 1 Enable PCS6#, active when I/O address between 600h..6FFh
    Bit 7..15 = don't care

Return Value

none

Comments

used pins:
    PCS[0..3]#, PCS[5..6]#
excluded pins:
    if PCS0#: ALE (multiplexed address / data bus)
    if PCS1#: A0, PIO4, TMRIN0
    if PCS2#: PIO6, INT2, INTA#, PWD, hw flow control serial port 1,
        cascaded interrupt controller
    if PCS3#: PIO5, INT4, hw flow control serial port 1
    if PCS5#: A[1..2], PIO3, TMROUT1, TMRIN1
    if PCS6#: A[1..2], PIO2

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Interrupt 0xA2 service 0x84: PFE: Enable External Interrupt Requests

Enable external interrupt requests INT[0], INT[2..6].

Parameters

AH: Must be 0x84.
DX: Mask
    Bit 0 = 1 Enable INT0
    Bit 1 = don't care
    Bit 2 = 1 Enable INT2
    Bit 3 = 1 Enable INT3
    Bit 4 = 1 Enable INT4
    Bit 5 = 1 Enable INT5
    Bit 6 = 1 Enable INT6
    Bit 7..15 = don't care

Return Value

none

Comments

used pins:
    INT0, INT[2..6]
excluded pins:
    if INT0: PIO13, TMROUT0, cascaded interrupt controller
    if INT2: PIO6, PCS2#, INTA#, PWD, hw flow control serial port 1
    if INT3: PIO12, serial port 1
    if INT4: PIO5, PCS3#, hw flow control serial port 1
    if INT5: PIO1, DRQ0, default I²C-Bus pins
    if INT6: PIO0, DRQ1, default I²C-Bus pins

Parameters

AH

Must be 0x85.

DX

Mode

Bit 0..1 = 10 Enable TMRIN0
= 11 Enable TMROUT0
Bit 2..3 = 10 Enable TMRIN1
= 11 Enable TMROUT1
Bit 4..15 = don't care

Return Value

none

Comments

If on a given timer the external input is selected, then that timer's external output is not available and vice-versa.

used pins:

TMRIN[0..1], TMROUT[0..1] excluded pins:

Parameters

AH

Must be 0x86.

AL

1 = active high, level-sensitive interrupt
0 = low-to-high, edge-triggered interrupt

DX

Mask, bits set to designate interrupts affected:

Return Value

none

Comments

Default for all interrupts is edge-triggered mode. In each case (edge or level) the interrupt pins must remain high until they are acknowledged.

Level-sensitive mode for INT5 / INT6 is not supported. The INT5 / INT6 interrupts operate only in edge-triggered mode.

Parameters

AH: Must be 0x87.

Return Value

none

Comments

In PWD mode, TMRIN0, TMRIN1, INT2 and INT4 are configured internal to the
chip to support the detection of rising (INT2) and falling (INT4) edges on the PWD
input pin and to enable either timer0 when the signal is high or timer1 when
the signal is low.   The INT4, TMRIN0 and TMRIN1 pins are not used in PWD mode
and so are available for use as PIO's.

The ISR for the INT2 and the INT4 interrupts should examine the current count of
the associated timer, timer1 for INT2 and timer0 for INT4, in order to determine
the pulse width.   The ISR should then reset the timer count in preparation for the
next pulse.

Overflow conditions, where the pulse width is greater than the maximum count of the
timer, can be detected by monitoring the MaxCount bit in the associated timer or by
setting the timer to generated interrupt requests.

used pins:
    PWD
excluded pins:
    TMRIN0, TMRIN1, TMROUT0, TMROUT1, INT4, INT2
    PCS2#, INTA#, PIO6, hw flow control serial port 1

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Interrupt 0xA2 service 0x88: PFE: Enable External DMA

Enables DRQ pin to start DMA transfer

Parameters

AH: Must be 0x88.
AL: DRQ channel:
0 = DRQ0
1 = DRQ1

Return Value

AX = 0 no error
AX = -1 invalid DRQ channel
AX = -2 DMA channel is used for serial interface

Comments

You must disable the serial port DMA mode to use external DMA.   This is done with a CHIP.INI entry.   The COM port uses DRQ1 and the EXT port uses DRQ0.

used pins:
    DRQ[0..1]
excluded pins:
    if DRQ0: PIO1, INT5, default I²C-Bus pins
    if DRQ1: PIO0, INT6, default I²C-Bus pins

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Interrupt 0xA2 service 0x89: PFE: Enable INT0 / INTA cascade mode

Enable INT0 / INTA cascade mode

Parameters

AH: Must be 0x89.

Return Value

none

Comments

To install a service interrupt routine in cascade mode, the
HAL function 0x84 "Install Interrupt Service Routine" can not be used, because
the cascaded interrupt controller supply the interrupt type over the bus.
Install a normal interrupt service routine (ISR) using the setvect function.
At the end of your ISR, issue an EOI to both the cascaded controller and to
the internal interrupt controller (INT0).

used pins:
INT0, INTA#
excluded pins:
PIO13, TMROUT0, INT0 in normal mode, PIO6, PCS2#, PWD, hw flow control serial port 1

Parameters

AH

Must be 0x8A.

AL

Bit 0-3

Bit 4-7

don't care

Return Value

none

Comments

Default for PCS0#-PCS3# are 15 wait states.

Parameters

AH: Must be 0x90.
ES:DI: Pointer to a HwApiFunctionStruct data structure which will be filled with vectors to @CHIP-RTOS Hardware API Functions.

Return Value

AX= -1 if size parameter was too large. The size field of the structure will be set in this case to the number of supported vectors.

AX= 0 on success

Comments

Note that the size member of the HwApiFunctionStruct serves as both an input and output parameter. The caller must set this value to the number of vectors to be filled into the data structure by this API call. In the event that this value exceeds the number of vectors available, the AX value returned will be -1 and this API will set the size to 2, which is the number of vectors available by this API's current implementation.

In any case, the resulting count in size indicates the number of vectors output to the caller's HwApiFunctionStruct data structure at [ES:DI] by this API call.

typedef struct

{

   int size; // number of function entries

   unsigned  (huge *readPios)(void);

   void      (huge *writePios)(unsigned);

} HwApiFunctionStruct;



// Example for usage:



int main()

{

  HwApiFunctionStruct hwApi;

  unsigned            pios;



  [...]

  hwApi.size = 2;          // space for two functions in the struct


  pfe_get_hwapi_func_ptr(&hwApi);



  hwApi.writePios(0x55);   // write something to the pios

  pios = hwApi.readPios(); // read something from the pios

  [...]

}

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Interrupt 0xA1 service 0x10: HAL: Set int0 Vector

Define the interrupt handler for the hardware interrupt 0

Parameters

AH: Must be 0x10
ES:DX: Pointer to your interrupt handler

Return Value

none

Comments

The interrupt handler should be defined as

void interrupt my_handler(void)

Interrupts are enabled upon entry into your routine.

There is no need to signal any end of interrupt. This is handled by the system after your handler performs it's return.

The stack size must be at least 400 bytes.

Do not use any floating point arithmetic in your interrupt service routine.

Developer Notes

This function is only for compatibility to older version of the hardware API.
Please use interrupt 0xA2 function 0x84 and interrupt 0xA1 function 0x84 instead.

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Interrupt 0xA1 service 0x80: HAL: Read Data Bus

Read from specified address.

Parameters

AH: Must be 0x80.
DI: Address
BX: wAND
CX: wXOR

Return Value

8 Bit data in ax, ax = (databus & wAND) ^ wXOR

Comments

& = bit wise AND
^ = bit wise XOR

The result is combined with wAND and wXOR parameters. To read the data bus without change, set wAND=0xFFFF and wXOR=0x0000.

Parameters

AH: Must be 0x81.
DI: Address
DL: 8 bit data
BX: wAND
CX: wXOR

Return Value

none

Comments

& = bit wise AND
^ = bit wise XOR

The provided parameters are combined as follows to form the output byte value:

output value = (data & wAND) ^ wXOR
To write the value in DL to the address without modification, set wAND=0xFFFF and wXOR=0x0000.

Parameters

AH: Must be 0x82.
BX: wAND
CX: wXOR

Return Value

ax = (PIO[0..13] & wAND) ^ wXOR.

Comments

& = bit wise AND
^ = bit wise XOR

The result is combined with the wAND and wXOR parameters. To read the PIO pins without modification, set wAND=0xFFFF and wXOR=0x0000. To read only the input pins, set wAND = wPIO & wINPUTS. The wPIO and wINPUTS values are return values from PFE function 0x82.

Parameters

AH

Must be 0x83.

DX

data applied to PIO[0..13]

BX

wAND

CX

wXOR

Return Value

none

Comments

& = bit wise AND
^ = bit wise XOR

Before the value is written, the value is combined with the wAND and wXOR parameters as:

PIO[0..13] = (data & wAND) ^ wXOR

To write value in DX to the programmable I/O pins without change, set wAND=0xFFFF and wXOR=0x0000.

Only PIO pins that are defined as outputs can be written.

Parameters

AH

Must be 0x84.

DH

Bit mask for the ISR type:

DL

HAL interrupt number from following list:

CX

Number of interrupts generated before new user interrupt service routine is called.
CX = 0 disables the user ISR (same as a NULL in ES:BX).

ES:BX

far pointer to user interrupt service routine
if pointer is NULL user ISR is disabled

Return Value

Far pointer to old handler in ES:BX

Comments

The user-defined ISR is called from a system ISR with the interrupt identifier number in the BX CPU register, thus allowing for a single user ISR to handle multiple interrupt sources. The user ISR can be declared in either of the following forms:

void huge My_ISR(void) ; // More efficient form

void interrupt My_ISR(void) ; // Tolerated form

The more efficient huge procedures are recommended. For assembly language ISR implementations, a far RET is recommended and a IRET on exit is tolerated. The user ISR function must preserve only the DS and BP registers, so there is no requirement for the full register save/restore provided by the interrupt declarations.

Any required EOI signal is issued by the system ISR which calls your user ISR function. This EOI is issued after your function returns.

If you install a RTX ISR you can use the following RTX calls in your ISR:

Important Notes:
A RTX ISR is slower than a normal ISR. RTX ISR are not recommended for INT5 or INT6 if DMA is used by the Fossil serial ports interface, because the slower RTX ISR could result in UART receiver character loss.

If you are using a RTX ISR for timer0, timer1, INT5 or INT6 there must not exist a normal ISR on the system which enables the interrupts during its execution! Do not install a RTX ISR for NMI.!

Also important : The NMI function of the multifunction pin 17 (RESET/NMI/LINK_LED) of the IPC@CHIP SC11/SC12/SC13 is for power fail purposes only. It is not possible to use NMI as a "normal" interrupt pin like INT0 for generating interrupts. It can only be used as described in the IPC@CHIP hardware documentation.

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Interrupt 0xA1 service 0x85: HAL: Initialize Timer Settings

Initialize the timer settings of timer0 or timer1.

Parameters

AH: Must be 0x85.
AL: Timer
0=Timer0 / 1=Timer1
DX: Mode
    Bit 0: 0=run single time / 1=run continuous
    Bit 1: 0=disable timer interrupt / 1=enable timer interrupt
    Bit 2: 0=use internal clock / 1=use TMRIN pin as external clock
    Bit 3..15: not used
CX: Clock divider (maximum count value)

Return Value

none

Comments

The clock divider value serves as a comparator for the associated timer count.   The timer count is a 16 bit value that is incremented by the processor internal clock (see HAL function 0x8A) or can also be configured to increment based on the TMRIN0 or TMRIN1 external signals (see PFE function 0x85).   The TMROUT0 und TMROUT1 signals can be used to generate waveforms of various duty cycles.   The default is a 50% duty cycle waveform   (Change waveform with HAL function 0x8B).

Note that TMRIN pin and TMROUT pin can not be used at the same time.

If the clock divider value is set to 0000h, the timer will count from 0000h to FFFFh (maximum divider).   When the timer reaches the clock divider value, it resets to 0 during the same clock cycle.   The timer count never dwells equals to the clock divider value (except for special case when divider value is set to 0000h).

When the timer is configured to run in single time mode, the timer clears the count and then halts on reaching the maximum count (clock divider value).

If the timer interrupt is enabled, the interrupt request is generated when the count equals the clock divider value.   Use HAL function 0x84 to install your interrupt service routine.

If "use internal clock" is selected the associated TMRIN pin serves as a gate.   A "high" on the TMRIN pin keeps the timer counting.   A "low" holds the timer value.

Developer Notes

The timer output frequency is dependent on the internal processor clock.
For compatibility with future versions of @Chip, please use the HAL function 0x8A, "Get frequencies", to compute the correct clock divider value.

Available examples
1. TimerIn example, timerin.c
2. TimerOut example, timerout.c

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Interrupt 0xA1 service 0x86: HAL: Start Timer

Enable the specified timer to count.

Parameters

AH: Must be 0x86.
AL: Timer
0=Timer0 / 1=Timer1

Return Value

none

Parameters

AH: Must be 0x87.
AL: Timer
0=Timer0 / 1=Timer1

Return Value

none

Comments

The specified timer is disabled.

Parameters

AH: Must be 0x88.
AL: Timer
0=Timer0 / 1=Timer1

Return Value

AX = Counter reading
DX = 1=MaxCount reached / 0=MaxCount not reached

Comments

AX contains the current count of the associated timer. The count is incremented by the processor internal clock (see HAL function 0x8A), unless the timer is configured for external clocking (then it is clocked by the TMRIN0 and TMRIN1 signals).

Parameters

AH: Must be 0x89.
AL: Timer
0=Timer0 / 1=Timer1
DX: Value to write to 16 bit counter

Return Value

none

Comments

The timer count can be written at any time, regardless of whether the corresponding timer is running.

Parameters

AH

Must be 0x8A.

AL

Which frequency to get:

Return Value

DX:AX frequency [Hz]

Comments

Use the timer base frequency to compute the correct timer clock divider value, where:

Output frequency = timer base frequency / clock divider

Use the maximum baud rate compute the correct baud rate for the processor specific baud rate initialize function (See Fossil Extended line control initialization function).

Baud rate = maximum baud rate / baud rate divider

Parameters

AH: Must be 0x8B.
AL: Which Timer
0=Timer0 / 1=Timer 1
DX: Mode
0=disable duty cycle / 1=enable duty cycle
CX: Alternate clock divider (if DX = 1)

Return Value

none

Comments

Use this function to modify the timer waveform behavior.   For example a 50% duty cycle waveform can be generated by specifying here an alternate clock divider value in CX that is the same value as was used for the main clock divider value set in the Timer Initialization function call.

Please note that the timer frequency will change if you use this function.   If you disable the duty cycle, the timer output will no longer generate a rectangle signal.   When duty cycle mode is disabled, the TMROUT pin switches low for only one clock cycle after the maximum count is reached.   If you want an alternate duty cycle waveform, compute it with the following formula:

Output frequency = Timer base frequency * 2
            / (divider high level + divider low level)

The divider high level is the divider set by the Timer Initialization function.   The divider low level is the alternate clock divider passed to this function in the CX register.

Parameters

AH: Must be 0x8C.
AL: IPC@CHIP PIO No. [0..13]

Return Value

AX=0 PIO pin is low, AX!=0 PIO pin is high

Parameters

AH: Must be 0x8D.
AL: IPC@CHIP PIO No. [0..13]
DX: DX = 0 ==> set PIO to low
DX non-zero ==> set PIO to high

Return Value

none

Parameters

AH: Must be 0x8E.
AL: Type (0=INT0 ... 4=INT4)

Return Value

none

Comments

When installing a interrupt service routine through HW API, it's not
necessary to call this function, because the HW API does it for you.
This function is provided for writing your own interrupt service routines without
the HAL function Install Interrupt Service Routine.

This function is especially needed for generating an EOI for INT0 when using cascaded
mode of the interrupt controller with INT0/INTA .

Parameters

AH: Must be 0x8F.
AL: Timer
0=Timer0 / 1=Timer1
DX: Mode
    Bit 0..2: must be 0
    Bit 3: 0=disable prescale t2 / 1=enable prescale t2
    Bit 4: 0=disable retrigger / 1=enable retrigger
    Bit 5..15: must be 0

Return Value

none

Comments

The Initialize Timer Settings function must be called prior to this function!

Prescale T2:

Get Frequencies

Retrigger:

Parameters

AH: Must be 0x90.
AL: Mode
    0 = only get mode
    2 = Watchdog will be triggered by user program
    3 = Watchdog will be triggered by @CHIP-RTOS (default)

Return Value

AX=mode

Comments

The watchdog timeout period is 800 ms.

If you select the User Program mode, you must call the HAL Refresh Watchdog function 0x91 at least every 800 ms to prevent the watchdog from resetting the system. In @CHIP-RTOS mode, the @CHIP-RTOS performs the watchdog strobing provided that the system's timer interrupt is allowed to execute. Beware that excessive interrupt masking periods can lead to system resets.

Parameters

AH: Must be 0x91.

Return Value

none

Comments

If the watchdog is in User Program mode, this function must be called at least every 800 ms to prevent a CPU reset due to watchdog timeout.

Parameters

AH

Must be 0x92.

AL

1=Mask, 0=Unmask

DX

HAL interrupt number from following list:

Return Value

none

Comments

Some interrupts share the same mask bit. If you mask one of them, the other interrupts which are assigned to the same bit are also masked. Here are the groups which are masked together:

CAUTION:

Masking any of the three timer interrupts will suspend the @CHIP-RTOS 1000 Hz real-time interrupt, essential for system operation. Consequently this mask period should be very brief, if used at all.

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Interrupt 0xA1 service 0xA0: HAL: Block Read Data Bus

Read block of bytes from data bus into provided buffer.

Parameters

AH: Must be 0xA0.
DI: First address
SI: Second address
ES:BX: Pointer to buffer
CX: Number of bytes to read into buffer

Return Value

none

Comments

IF SI != DI, this function will alternate reads between the two addresses until CX bytes are read, starting at first address. Set SI == DI if you want to read from only a single address.

Parameters

AH: Must be 0xA1.
DI: First address
SI: Second address
ES:BX: Pointer to buffer
CX: Number of bytes in buffer to output

Return Value

none

Comments

IF SI != DI, this function will alternate between writes to first and second address. Set SI == DI if you want all data written to a single address.

Parameters

AH

Must be 0xB0

AL

DMA channel:
0 = DRQ0
1 = DRQ1

CX

Number of bytes which has to be transferred

DX

Control Register:
    Bit 0: 1=Priority for the channel / 0=Priority for the other channel
    Bit 1: 1=Source synchronized / 0=No source synchronization
    Bit 2: 1=Destination synchronized / 0=No destination synchronization
    Bit 3: 1=Use interrupt at end of transfer / 0=do not use an interrupt
    Bit 4: must be set to '1'
    Bit 5: 1=Source address increment / 0=No increment of source address
    Bit 6: 1=Source address decrement / 0=No decrement of source Address
    Bit 7: 1=Source is in memory space / 0=Source is in IO space
    Bit 8: 1=Destination address increment / 0=No increment of destination address
    Bit 9: 1=Destination address decrement / 0=No decrement of destination address
    Bit 10: 1=Destination is in memory space / 0=Destination is in IO space
    Bit 11: 1=Word Transfer / 0=Byte Transfer

Bit1 and Bit2 can't be set at the same time.

BX:SI

Pointer to unsigned long (20-Bit physical) source address

ES:DI

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