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@CHIP-RTOS C Library V2.06 - Hardware API


pfe_enable_pwd

Enable Pulse Width Demodulation (PWD)

void pfe_enable_pwd ( void );

Parameters

-- none --

Return Value

-- none --.

Comments

In PWD mode, TMRIN0, TMRIN1, INT2 and INT4 are configured internal to the chip to support the detection of rising (INT2) and falling (INT4) edges on the PWD input pin and to enable either TIMER0 when the signal is high or TIMER1 when the signal is low.   The INT4, TMRIN0 and TMRIN1 pins are not used in PWD mode and so are available for use as PIO's.

The ISR for the INT2 and the INT4 interrupts should examine the current count of the associated timer, TIMER1 for INT2 and TIMER0 for INT4, in order to determinate the pulse width.   The ISR should then reset the timer count in preparation for the next pulse.

Overflow conditions, where the pulse width is greater than the maximum count of the timer, can be detected by monitoring the MaxCount bit in the associated timer or by setting the timer to generated interrupt requests.

Used pins:
    PWD

Excluded pins:
    TMRIN0, TMRIN1, TMROUT0, TMROUT1, INT4, INT2
    PCS2#, INTA#, PIO6, hw flow control serial port 1

RTOS API

This library function invokes a RTOS software interrupt. Refer to this RTOS API function's documentation for more details.

Supported since or modified in @CHIP-RTOS version

    SC12SC13SC11SC1x3
    V1.00V1.00V1.00n/a

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