@CHIP-RTOS C Library V2.06 - Hardware API
pfe_enable_pcs
Enable chip selects PCSx# void pfe_enable_pcs ( unsigned char pcs ); SC1x Parameters
- pcs
- Chip select number:
0: Enable PCS0#, active when I/O address between 000h..0FFh
1: Enable PCS1#, active when I/O address between 100h..1FFh
2: Enable PCS2#, active when I/O address between 200h..2FFh
3: Enable PCS3#, active when I/O address between 300h..3FFh
4: N/A
5: Enable PCS5#, active when I/O address between 500h..5FFh
6: Enable PCS6#, active when I/O address between 600h..6FFh
SC1x3 Parameters
- pcs
- Chip select number:
0: don't care (PCS0# is no PIO), PCS0# is active when I/O address between 000h..1FFh
1: don't care (PCS1# is no PIO), PCS1# is active when I/O address between 200h..3FFh
2: don't care (PCS2# is no PIO), PCS2# is active when I/O address between 400h..5FFh
3: don't care (PCS3# is no PIO), PCS3# is active when I/O address between 600h..7FFh
4: Enable PCS4#, active when I/O address between 800h..9FFh
5: Enable PCS5#, active when I/O address between A00h..BFFh
6: Enable PCS6#, active when I/O address between C00h..DFFh
7: Enable PCS7#, active when I/O address between E00h..FFFh
Return Value
- -- none --.
SC1x Comments- Used pins:
PCS[0..3]#, PCS[5..6]#
Excluded pins:
if PCS0#: ALE (multiplexed address / data bus)
if PCS1#: A0, PIO4, TMRIN0, SPI
if PCS2#: PIO6, INT2, INTA#, PWD, SPI, hw flow control serial port 1,
cascaded interrupt controller
if PCS3#: PIO5, INT4, SPI, hw flow control serial port 1
if PCS5#: A[1..2], PIO3, TMROUT1, TMRIN1
if PCS6#: A[1..2], PIO2
SC1x3 Comments- Used pins:
PCS[0..7]#
Excluded pins:
If PCS4#: PIO4
If PCS5#: PIO3
If PCS6#: PIO2
If PCS7#: PIO5
See Also
RTOS API
- This library function invokes a RTOS software interrupt.
Refer to this RTOS API function's
documentation
for more details.
Supported since or modified in @CHIP-RTOS version-
SC12 | SC13 | SC11 | SC1x3 |
-
V1.00 | V1.00 | V1.00 | V0.90 |
This API List
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